In this paper, we discuss the device, circuit and system design of a closed loop accelerometer sensor using an in-plane movable suspended gate FET. The paper is comprehensive and discusses device architecture, simulation methods adopted (we use the Look-up-table method we reported in paper 9 below), circuit design for the sensor, and a suggested fabrication plan for the sensor. Interface circuits involve novel re-configurable charge pumps for driving actuators in closed loop operation. We use fully differential architecture which requires two charge pumps for generating differential actuator drive along with a high voltage common mode feedback circuit. All circuits are designed in a standard low voltage CMOS process.

A rigorous analyis of the effect of jitter on the settling time of mesochronous clock re-timing circuits is presented in this paper. The dependence of settling time on jitter was first reported by us in ISCAS 2017 conference. This dependence was experimentally verified with measurements performed on a test chip. Markov models are developed for different types of jitter and their predictions were verified using simulations in Verilog-A. A few techniques of designing fast settling mesochronous retiming circuits are then presented.