In this paper, we discuss the device, circuit and system design of a closed loop accelerometer sensor using an in-plane movable suspended gate FET. The paper is comprehensive and discusses device architecture, simulation methods adopted (we use the Look-up-table method we reported in paper 9 below), circuit design for the sensor, and a suggested fabrication plan for the sensor. Interface circuits involve novel re-configurable charge pumps for driving actuators in closed loop operation. We use fully differential architecture which requires two charge pumps for generating differential actuator drive along with a high voltage common mode feedback circuit. All circuits are designed in a standard low voltage CMOS process.
@article{pramod_sesors22,author={Martha, Pramod and Ganga, K. M. and Sebastian, Anju and Seena, V. and Kadayinti, Naveen},journal={IEEE Sensors Journal},title={A Closed-Loop In-Plane Movable Suspended Gate FET (CLIP-SGFET) Sensor With a Dynamically Reconfigurable Charge Pump},year={2022},volume={22},number={22},pages={21550-21560},doi={10.1109/JSEN.2022.3210646},}
2021
IEEE TED
CMOS-MEMS Accelerometer With Stepped Suspended Gate FET Array: Design & Analysis
In this paper we analyze the effect of pull-in instability in out-of-plane movable gate FET based MEMS sensors. Pull-in instability limits the maximum displacement dynamic range of such devices to 1/3rd of the initial air-gap of the transistor. We propose a stepped suspended gate FET sensor that allows increasing the dynamic range up to 50% of the initial airgap, with the same device sensitivity. This also results in a 90% increase in the pull-in voltage. We present the analysis of the stepped-suspended gate FET along with design and simulation of the device.
@article{pramod-ted21,author={Martha, Pramod and Kadayinti, Naveen and Seena, V.},journal={IEEE Transactions on Electron Devices},title={{CMOS-MEMS} Accelerometer With Stepped Suspended Gate {FET} Array: Design \& Analysis},year={2021},volume={68},number={10},pages={5133-5141}}
IEEE Sensors
A CMOS-MEMS Accelerometer With U-Channel Suspended Gate SOI FET
Suspended gate transistors can be used as inertial sensors, wherein the displacement of the gate relative to the channel can be sensed and used as a measurement of acceleration. In these transistors, the gate is physically far from the channel (few 100’s of nm at least) which results in poor gate control over the channel, affecting its performance. This is very similar to short channel effects which happen in scaled MOSFETs. However, unlike MOSFETs for which short channel effects start becoming apparent at lengths of sub 100 nm, for suspended gate FETs these effects are significant even for channel lengths of a few μm due to poor gate control. In this paper, we show how these “Pseudo-short-channel” effects can be reduced by using a U-channel SOI FET.
@article{pramod_sesors21,author={Martha, Pramod and Kadayinti, Naveen and Seena, V.},journal={IEEE Sensors Journal},title={A {CMOS-MEMS} Accelerometer With {U}-Channel Suspended Gate {SOI FET}},year={2021},volume={21},number={9},pages={10465-10472},doi={10.1109/JSEN.2021.3060186}}
2019
Springer AICSP
Effect of jitter on the settling time of mesochronous clock retiming circuits
N.
Kadayinti, Amitalok J.
Budkuley, Maryam S.
Baghini, and Dinesh K.
Sharma
Analog Integrated Circuits and Signal Processing, 2019
A rigorous analyis of the effect of jitter on the settling time of mesochronous clock re-timing circuits is presented in this paper. The dependence of settling time on jitter was first reported by us in ISCAS 2017 conference. This dependence was experimentally verified with measurements performed on a test chip. Markov models are developed for different types of jitter and their predictions were verified using simulations in Verilog-A. A few techniques of designing fast settling mesochronous retiming circuits are then presented.
@article{nav-spring18,author={Kadayinti, N. and Budkuley, Amitalok J. and Baghini, Maryam S. and Sharma, Dinesh K.},title={Effect of jitter on the settling time of mesochronous clock retiming circuits},journal={Analog Integrated Circuits and Signal Processing},year={2019},volume={101},number={3},pages={623-640},issn={1573-1979},doi={10.1007/s10470-018-1344-9},}
2018
Elsevier MEJ
Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects
N.
Kadayinti, Maryam
Shojaei Baghini, and Dinesh K.
Sharma
A new type of clock retiming circuit that performs coarse+fine correction for clock retiming was proposed by us in International Conference on VLSI Design in 2017. This paper reports detailed measurements of this circuit quantifying the performance of the same. In particular, the effects of different types of jitter are demonstrated which show the robustness of this circuit. The circuit on which the measurements were performed was fabricated in UMC 130 nm CMOS technology.
@article{nav1-mej18,title={Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects},journal={Microelectronics Journal},volume={81},pages={101 - 106},year={2018},issn={0026-2692},doi={https://doi.org/10.1016/j.mejo.2018.09.011},author={Kadayinti, N. and {Shojaei Baghini}, Maryam and Sharma, Dinesh K.},keywords={Repeaterless interconnects, Low swing interconnect, Clock data recovery, Mesochronous synchronizers}}
2017
Elsevier MEJ
Sense amplifier comparator with offset correction for decision feedback equalization based receivers
In this paper, a decision feedback circuit with integrated offset compensation is proposed. The circuit is built around the sense amplifier comparator. The feedback loop is implemented using a switched capacitor network that picks from one of two pre-computed voltages to be fed back, which results in minimum latency. The circuit was fabricated and tested in 130 nm CMOS.
@article{nav-mej17,title={Sense amplifier comparator with offset correction for decision feedback equalization based receivers},journal={Microelectronics Journal},volume={70},pages={27 - 33},year={2017},issn={0026-2692},doi={https://doi.org/10.1016/j.mejo.2017.10.006},author={Kadayinti, N. and Sharma, Dinesh K.},keywords={Decision feedback, Loop latency, Loop unrolling, Low swing interconnect, Bandwidth enhancement, Offset compensation},url={http://www.sciencedirect.com/science/article/pii/S002626921730071X}}
Conference papers
2023
APSCON
CMOS-MEMS Nano Force Sensor with Sub-μm U-Channel Suspended Gate SOIFET
Pramod
Martha, Naveen
Kadayinti, and V.
Seena
In 2023 IEEE Applied Sensing Conference (APSCON) , 2023
This article presents a novel sub-μm U-channel suspended gate SOIFET (USG-SOIFET) based nano-force sensor. The paper discusses how U-channel can mitigate pseudo short channel effects present in suspended gate FET (SGFET). USGFETs with channel length as low as 0.95 µm with an air-gap of 200 nm are shown. This helps in improving the sensitivity of USG-SOIFET and makes it a suitable candidate to detect forces in the nano-newton range. The air-gap values for different forces are obtained from the finite element method (FEM) simulation of MEMS structure and used as input to TCAD for USG-SOIFET simulations to get the final sensor response.
@inproceedings{pramod_apscon23,author={Martha, Pramod and Kadayinti, Naveen and Seena, V.},booktitle={2023 IEEE Applied Sensing Conference (APSCON)},title={{CMOS-MEMS} Nano Force Sensor with Sub-\mu m {U}-Channel Suspended Gate {SOIFET}},year={2023},volume={},number={},pages={1-3},doi={10.1109/APSCON56343.2023.10101320}}
APCCAS
Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs
Mayur S.
Marinaik, and Naveen
Kadayinti
In 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2023
A technique for calibrating a negative conductance load for impedance cancellation in high gain OTAs is presented in this paper. The basic principle of tuning this negative conductance load is by minimising the steady state error of the OTA that is configured in closed loop in calibration mode. Here the calibration of the negative conductance load is done with the OTA itself and it does not need any replica. This avoids the problem of over-correction due to mismatch.
@inproceedings{10509952,author={Marinaik, Mayur S. and Kadayinti, Naveen},booktitle={2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)},title={Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs},year={2023},volume={},number={},pages={363-366},keywords={Circuits and systems;Simulation;Asia;Calibration;Steady-state;Impedance;Gain;High gain OTA;negative conductance;impedance cancellation},doi={10.1109/APCCAS60141.2023.00087}}
2022
ISCAS
A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters
Mayur S.
Marinaik, Ganga K.
Maheshwarappa, and Naveen
Kadayinti
In 2022 IEEE International Symposium on Circuits and Systems (ISCAS) , 2022
A Gm-C based variable bandwidth all pass filter (APF) as true time delay element is presented in this paper. A cascade of low order APF’s is used whose group delay is varied by modulating the Gm of its constituent transconductors. This method avoids the need for high quality varactors, and does not require a large range of capacitance values resulting in design simplicity and reduced power consumption. The proposed design is implemented in TSMC 65 nm technology. Simulation results show that the delay element with 3 stages of third order APF maintains uniform magnitude response with the delayrange-bandwidth product of 0.8 and power/delay-range factor of 0.04 mW/ps upto bandwidth of 1 GHz.
@inproceedings{naveen_iscas22,author={Marinaik, Mayur S. and Maheshwarappa, Ganga K. and Kadayinti, Naveen},booktitle={2022 IEEE International Symposium on Circuits and Systems (ISCAS)},title={A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters},year={2022},volume={},number={},pages={3473-3477},doi={10.1109/ISCAS48785.2022.9937466}}
2021
INERTIAL
A Technique for Modeling and Simulating Transistor Based MEMS Sensors
Pramod
Martha, Anju
Sebastian, V.
Seena, and Naveen
Kadayinti
In 2021 IEEE International Symposium on Inertial Sensors and Systems (INERTIAL) , 2021
Design of transistor based MEMS sensors (like suspended gate transistors) is quite challenging due to the diverse phenomena involved in their operation. The sensor’s output depends on the mechanical structure of the device, the process steps used for the transistor fabrication, and of course - the circuit in which the transistor is used. In this paper, we show how we can design and simulate such a transistor using standard tools for (i) mechanical design, (ii) MOSFET process simulation, (iii) MOSFET device simulation and (iv) circuit simulation; by using a look-up-table model based approach for interfacing the different domain analyses. An example design of an accelerometer sensor with a vertically movable gate transistor is designed and simulated to demonstrate the proposed modeling technique.
@inproceedings{pramod_inertial21,author={Martha, Pramod and Sebastian, Anju and Seena, V. and Kadayinti, Naveen},booktitle={2021 IEEE International Symposium on Inertial Sensors and Systems (INERTIAL)},title={A Technique for Modeling and Simulating Transistor Based {MEMS} Sensors},year={2021},volume={},number={},pages={1-2},doi={10.1109/INERTIAL51137.2021.9430485}}
2017
ISCAS
Settling time of mesochronous clock re-timing circuits in the presence of timing jitter
N.
Kadayinti, A. J.
Budkuley, and D. K.
Sharma
In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) , 2017
In this work, we investigate the effect of timing jitter on the settling time of mesochronous clock re-timing circuits. While the effect of jitter on the BER of synchronizers had been well studied, its effect on settling time had not received attention. The synchronizer system is modeled as a 1 dimensional Markov chain and used to analyze different types of jitter. The paper also proposes techniques of reducing the settling time.
@inproceedings{naveen_iscas17,author={Kadayinti, N. and {Budkuley}, A. J. and {Sharma}, D. K.},booktitle={Proc. IEEE Int. Symp. Circuits and Systems (ISCAS)},title={Settling time of mesochronous clock re-timing circuits in the presence of timing jitter},year={2017},volume={},number={},pages={1-4},url={https://doi.org/10.1109/ISCAS.2017.8050694}}
VLSID
A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects
In this paper we reported a clock retiming circuit for low swing interconnects. The design uses a coarse + fine phase correction scheme. The coarse phase correction is done using a DLL and a control loop that picks the phase closest to the center of the data eye. The fine correction is performed using a VCDL which generates the actual sampling clock. Clock domain transfer from the sampling clock to the receiver clock domain is included in the design. The circuit was fabricated and tested in 130 nm CMOS.
@inproceedings{naveen_vlsi17,author={Kadayinti, N. and Baghini, M.S. and Sharma, D.K.},booktitle={Proc. 30th IEEE Conf. VLSI Design},title={A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects},year={2017},pages={15-20},url={https://doi.org/10.1109/VLSID.2017.12}}
VLSID
Clock Skew Measurement using an All-Digital Sigma-Delta Time to Digital Converter
A technique for measuring clock skew between two remote nodes in a chip is reported in this paper. Sub-sampling is used to generate time amplified signals with amplified skew. Since timing variations are typically very slow, this ends up oversampling the skew between the input clocks. Using this oversampling in the converter, a Delta-Sigma Time to Digital converter is constructed. The paper also discusses an all digital implementation of this concept, with negligible penalty in performance.
@inproceedings{mahadev_vlsi17,author={Shirwaikar, M. and Kadayinti, N. and Sharma, D.K.},booktitle={Proc. 30th IEEE Conf. VLSI Design},title={Clock Skew Measurement using an All-Digital Sigma-Delta Time to Digital Converter},year={2017},pages={321-326},url={https://doi.org/10.1109/VLSID.2017.41}}
2016
DATE
Testable design of repeaterless low swing on-chip interconnect
N.
Kadayinti, and D. K.
Sharma
In Proc. Design, Automation and Test in Europe (DATE) , Mar 2016
Testability is very important for high volume VLSI designs. Repeaterless low swing interconnects have been shown to be a promising alternative to repeater inserted links for continued interconnect performance scaling. However, these techniques use low swing and mixed signal circuits and their testability is not straightforward. We have reported some simple techniques for testing these mixed signal circuits using techniques established for testing digital circuits, like scan test and BIST with digital I/O’s. The fault coverage is evaluated for an example design.
@inproceedings{naveen-date16,author={Kadayinti, N. and Sharma, D. K.},booktitle={Proc. Design, Automation and Test in Europe (DATE)},title={Testable design of repeaterless low swing on-chip interconnect},year={2016},pages={563-566},month=mar,url={http://ieeexplore.ieee.org/document/7459375/}}
2013
VLSID
A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect
N.
Kadayinti, M.
Dave, M.S.
Baghini, and D.K.
Sharma
This paper reports a 2-tap capacitively coupled feedforward equalizer. A direct coupled weak driver allows arbitrarily low data activity factors. A detailed analysis of the architecture and a fast design method for designing the circuit using worst case sequences is also discussed in the paper.
@inproceedings{naveen_vlsi13,author={Kadayinti, N. and Dave, M. and Baghini, M.S. and Sharma, D.K.},booktitle={Proc. 26th IEEE Conf. VLSI Design},title={A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect},year={2013},pages={215-220},url={https://doi.org/10.1109/VLSID.2013.190}}
Patents
2023
Indian Patent
Closed Loop In-Plane Movable Suspended Gate FET based Accelerometer and The Fabrication Method Thereof
Seena V, Anju
Sebestian, and N.
Kadayinti
2023
Indian patent granted in Oct. 2023. Patent number: 456720
2020
Indian Patent
A Circuit for Expanding, Compressing or Delaying
an Electronic Pulse
N.
Kadayinti, and Mayur
Shivamurthy
2020
Indian patent application filed in May 2020. Application no. 202041019813.
Preprints
2020
ArXiv
Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits
This paper shows how the input offset of sampling flip-flops in the Alexander phase detector affects the jitter transfer from data to the recovered clock in a clock data recovery circuit. It is shown how the offset of the sampling flip-flop that samples the data at its transitions influences the jitter transfer from data to the recovered clock. Importantly, it is shown that zero offset is not always the best case. The effect is studied for different levels of data dependent jitter. The paper also discusses a tracking circuit that keeps the offset at the minimum jitter point.
@article{nav-cdr20,author={Kadayinti, N. and Baghini, M.S. and Sharma, D.K.},title={Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits},year={2020},url={https://arxiv.org/abs/2001.03553},}
A Closed-Loop In-Plane Movable Suspended Gate FET (CLIP-SGFET) Sensor With a Dynamically Reconfigurable Charge PumpIEEE Sensors Journal, 2022
CMOS-MEMS Accelerometer With Stepped Suspended Gate FET Array: Design & AnalysisIEEE Transactions on Electron Devices, 2021
A CMOS-MEMS Accelerometer With U-Channel Suspended Gate SOI FETIEEE Sensors Journal, 2021
CMOS-MEMS Nano Force Sensor with Sub-μm U-Channel Suspended Gate SOIFETIn 2023 IEEE Applied Sensing Conference (APSCON) , 2023
Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAsIn 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2023
A Technique for Modeling and Simulating Transistor Based MEMS SensorsIn 2021 IEEE International Symposium on Inertial Sensors and Systems (INERTIAL) , 2021
Clock Skew Measurement using an All-Digital Sigma-Delta Time to Digital ConverterIn Proc. 30th IEEE Conf. VLSI Design , 2017
