Talk on "Sub-sampling CMOS Frontends for Multistandard Reconfigurable RF Radios"

Speaker: Dr. Vijay Sankara Rao

Title: Sub-sampling CMOS Frontends for Multistandard Reconfigurable RF Radios

Abstract:With the evolution of wireless systems, more communication standards are being proposed while maintaining backward compatibility, therefore, there is an ever growing need for wideband multi-standard receivers similar to the software defined radio (SDR). For many years now, SDR or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success. In this talk, an intermediate solution to SDR receiver implementation called “Mini-SDR” architecture is discussed by exploiting the concept of bandpass sampling. Based on the proposed Mini-SDR architecture, three CMOS radio frontends are discussed: (1) a standalone electronic attack (EA) transceiver system, (2) dynamically reconfigurable multi-standard subsampling (DRMS) radio receiver and (3) a dual- band subsampling receiver for IEEE WLAN 802.11ac standard.The first architecture is a single chip integrated transceiver for a standalone EA system based on digital radio frequency memory (DRFM) repeater without the need for a separate instantaneous frequency measurement (IFM) receiver. This work reports the first sub-Nyquist bandpass sampling based single chip architectural solution for a standalone EA system where RF frontend and digital controller are integrated into the system. The second architecture is the DRMS radio receiver. The proposed receiver has a unique capability to detect the carrier frequency of the incoming signal, estimate its bandwidth and standard. The complete receiver architecture has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS and WLAN). The third architecture is the first dual-band subsampling receiver with subsampling frequency optimization to meet ultimate receiver error vector magnitude (EVM) of −40 dB. This IEEE 802.11ac WLAN dual-band subsampling receiver test-chip implemented in 1.2V 65-nm CMOS technology to prove the proposed concepts, including major system level, circuit level and layout level optimizations. This talk concludes with the success story of “Mini-SDR”.

Speaker Bio: Dr. Vijaya Sankara Rao Pasupureddi held a tenured Associate Professorship until March, 2019 at the Department of Integrated Systems and Circuits Design, School of Engineering and IT, Carinthia University of Applied Sciences (CUAS), Austria, Western Europe and now, Dr. Vijay Sankar is a tenured Professor Designate from August, 2019 in the same department along with the research partnership from Silicon Austria Labs. Currently, until August, 2019, he is teaching at the Centre for Advance Studies in Electronics Science and Technology, University of Hyderabad on leave from CUAS, Austria. Previously, Dr. Vijay Sankar was a Post-Doctoral Scientist with the Microelectronic Systems Laboratory, Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland. From 2011 to 2015, he was an Assistant Professor with the Department of Electrical Engineering, IIT Ropar and the Centre for VLSI Design and Embedded Systems, IIIT Hyderabad. He received his Ph.D. degree from the Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, India. He has published his research in reputed IEEE Transactions including TCAS-1, TAES and in flagship IEEE conferences including ESSSCIRC, VLSI Symposium etc., He has guided PhD, MS (by Research), MS (Engg.) and MTech students towards completion of their degrees and Dr. Vijay Sankar have been consistently ranked high for his excellence in teaching. He has been a Principal Investigator for numerous research and consultancy projects of approximate worth of INR. 5 Crores. His research interests include RF IC Design, Digital IC Design, Analog and Mixed Signal IC Design. He is currently an Editorial Board Member of the Journal of Low Power Electronics and Applications, MDPI (Basel, Switzerland).

Event Date: 27th June, 2019(Thrusday)

Event Time: 02:30 PM

Venue: Room No 115
IIT Dharwad, Karnataka

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